In many multimedia and digital signal processing (DSP) applications, for example, multiplication operations have a fixed-width property. This property means that input data and output results for multiplication operations have the same bit width. In these applications, multiplication by a W-bit constant multiplier is typically carried out using fixed-width constant multiplier systems and methods. In fixed-width constant multiplier systems and methods, the partial product terms corresponding to the nonzero bit positions in the constant multiplier are added to form the desired product.
In many fixed-width constant multiplier systems and methods, in order to implement the fixed-width property the “2W−1” bit product obtained from a W-bit multiplicand and a W-bit multiplier is quantized to W-bits by eliminating the “W−1” least-significant bits. This quantization, however, results in truncation errors that make these systems and methods unsuitable for many applications. Improved fixed-width multiplier schemes and/or designs such as, for example, Baugh-Wooley multipliers or parallel array multipliers exist. (See, e.g., S. S. Kidambi et al., “Area-efficient multipliers for digital signal processing applications,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 90–94 (February 1996); J. M. Jou and S. R. Kuang, “Design of a low-error fixed-width multiplier for DSP applications,” Electron. Lett., vol. 33, no. 19, pp. 1597–1598 (1997); L. D. Van et al., “Design of the lower error fixed-width multiplier and its applications,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 1112–1118 (October 2000); and S. J. Jou and H. H. Wang, “Fixed-width multiplier for DSP application,” in Proceedings of 2000 ICCD (Austin, Tex.), pp. 318–322 (September 2000); each of which is incorporated herein in its entirety.) These improved fixed-width multipliers, which implement the fixed-width property, operate by introducing biases into retained adder cells in order to compensate for the omitted “W−1” least-significant bits. Each of these improved fixed-width multiplier schemes and/or designs, however, still introduces errors into the multiplication output results, which for certain applications are significant.
Consider, for example, Kidambi et al. Kidambi et al. relates to a constant bias scheme wherein a constant bias is added to the retained cells. This constant bias scheme cannot be adjusted adaptively by the input signals, however, and the resulting truncation error is typically large. In Jou and Kuang and in Van et al., error compensation biases are generated using an indexing scheme. The indices used in these schemes attempt to incorporate the effects of the input signals and thus are an improvement over Kidambi et al. However, although quantization errors may be reduced by using indices, these schemes still have limitations that introduce errors into the multiplication output results, which for certain applications are significant. In Jou and Wang, statistical analysis and linear regression analysis are used to generate a bias that is added to retained adder cells. This scheme, however, also introduces errors into the multiplication output results, which for certain applications are significant. Thus, there is a need for new schemes and/or designs that do not have the limitations of the conventional schemes and/or designs.
What is needed is a new lower-error fixed-width multiplier, and a method for designing the same, that overcomes the limitations of the conventional fixed-width multiplier schemes and/or designs.